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| W81C180 USB HUB CONTROL INTERFACE GENERAL DESCRIPTION W81C180 implements a medium speed (12Mhz) Universal Serial Bus (USB) hub control interface. It supports four downstream ports and an I2C serial interface to microcontrollers. W81C180 acts as a USB hub controller and a hub repeater at the direction of an external microcontroller. W81C180 controls the traffic among the host, four downstream ports, and the microprocessor. As a hub controller, it can enable/disable ports, send and receive resets, and detect devices of high or low speeds. The W81C180 contains two function endpoints and two hub endpoints to allow both USB Control and Interrupt Transfers between the host and microcontroller. W81C180 is a compound USB device (hub with embeded function attached) with totally five downstream ports. Four of them are removable and the other is permanently attached to the microprocessor connected. W81C180 can be used as a hub controller in a standalone hub with attached function or in a microcontroller based USB device with hub functionality. In the latter case, the microcontroller does not need a USB interface and does not occupy one downstream port. FEATURES * Full compliance with USB spec Rev 1.0 and HID Class Definition Rev 1.0 * Support multiple endpoints for standalone hub with attached function * Support USB device with embedded hub functionality * USB function controller * USB hub controller/repeater * Bus-powered/self-powered hub option * Four downstream ports with per port overcurrent protection * Two endpoints for hub (Control and Interrupt) * Two endpoints for attached device (Control and Interrupt) * 6KV ESD protection * 32-pin PDIP * 5V CMOS device -1- Publication Release Date: May 1997 Revision A1 W81C180 USB BLOCK DIAGRAM: The Serial Interface Engine (SIE) controls the USB data flow between the uCs and the USB bus. Port0 is a high speed (HS) transceiver for the upstream data path. The Hub Repeater is the traffic controller which directs the bus data to and from the correct paths. The hub Controller and Function Controller determines what data is to be written to or read from the various FIFOs. The Bus Controller directs the interface between the uC and the W81C180. UPSTREAM PORT TRANCEIVER PORT 0 SERIAL INTERFACE ENGINE HUB REPEATER HUB CONTROLLER FUNCTION CONTROLLER TRANCEIVER PORT 1 TRANCEIVER PORT 2 TRANCEIVER PORT 3 TRANCEIVER PORT 4 USB FIFOs BUS CONTROLLER DOWNSTREAM DEVICES MICROCONTROLLER -2- Publication Release Date:May 1997 Revision A1 W81C180 PIN CONFIGURATION: 32 Pin PDIP V33U D0M D0P VDD IX2 IX1 OCP1 VBUS VREF OCP2 OCP3 OCP4 NPEN4 NPEN3 NPEN2 NPEN1 1 32 30 5 GNDU D4P D4M GND34 D3P D3M V33D D2P D2M GND12 D1P D1M VSS MDA MCL NINT 25 10 20 15 16 17 PIN DESCRIPTION: PIN # 1 2 3 4 5 6 7 8 9 10 11 NAME V33U D0M D0P VDD X2 X1 OCP1 VBUS VREF OCP2 OCP3 TYPE Power UI/O UI/O Power OUTPUT INPUT INPUT INPUT INPUT INPUT INPUT DESCRIPTION Voltage 3.3V to Upstream Transceiver USB upstream port, negative connection USB upstream port, positive connection Analog/Digital Voltage 5V Crystal connection Crystal input (12 MHz) Analog connection for Downstream Port1 Overcurrent Status Vcc from the upstream port Comparator reference voltage with all OCPs, Maximum reference voltages is 4.1V. Analog connection for Downstream Port2 Overcurrent Status Analog connection for Downstream Port3 Overcurrent Status -3- Publication Release Date: May 1997 Revision A1 W81C180 PIN DESCRIPTION, continued PIN # 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 NAME OCP4 NPEN4 NPEN3 NPEN2 NPEN1 NINT MCL MDA VSS D1M D1P GND12 D2M D2P V33D D3M D3P GND34 D4M D4P GNDU TYPE INPUT OUTPUT OUTPUT OUTPUT OUTPUT I/OD I/OD I/OD Ground UI/O UI/O Ground UI/O UI/O Power UI/O UI/O Ground UI/O UI/O Ground DESCRIPTION Analog connection for Downstream Port4 Overcurrent Status Power switch of Downstream Port4 Power switch of Downstream Port3 Power switch of Downstream Port2 Power switch of Downstream Port1 Enabled when valid data is received or a port changed occurred.(open drain) Serial clock from uC (open drain) Serial data to/from uC (open drain) Analog/Digital Ground USB downstream port1, negative connection USB downstream port1, positive connection D1/D2 Transceiver Ground USB downstream port2, negative connection USB downstream port2, positive connection 3.3V supply for downstream Transceivers USB downstream port3, negative connection USB downstream port3, positive connection D3/D4 Transceiver Ground USB downstream port4, negative connection USB downstream port4, positive connection Upstream Transceiver Ground -4- Publication Release Date:May 1997 Revision A1 W81C180 FIRST IN FIRST OUT STORAGE (FIFO'S): The W81C180 has five FIFO's, one receiving register. FIFO SRAM or SIZE* 32 32 1 32 NOTES Data received on Port0 which contains the correct address and pids will be stored here for the uC to read. The uC writes the data here which will be sent to the host when the correct address and pids are transmitted by the host. Data received on Port1 which contains the ack pid from host responds to the transmitted by W81C180 will be stored here for the uC to read. The uC writes the data here which will be sent to the host when the correct address and pids are transmitted by the host. The uC writes the data here which will be sent to the host when the correct address and pids are transmitted by the host. Endpt 0 Receiving Endpt 0 Transmitting Endpt 1 Receiving Endpt 1 (Hub) Transmitting Endpt 1 (Function) Transmitting 32 *: byte unit, maximum capability INTERFACE TO THE MICROCONTROLLER: The W81C180 communicates with the uC via a 2 wire bus. One signal is the data and the other the clock. The clock is always generated by the uC. The data is bi directional. After each byte of data (MSB first) an acknowledge bit (MDA=0) is sent by the receiver. The uC always initiates the communication with a start condition (MDA from 1 change to 0 while MCL=1) and the W81C180's address. The uC ends the transmission with a stop condition (MDA from 0 change to 1 while MCL=1). Data is always changed while MCL=0 and clocked in on the rising edge of MCL. The W81C180 acts as a slave memory device at address E8h. W81C180'S ADDRESS 1110 100S READ FROM W81C180 S=1 WRITE TO W81C180 S=0 The format for describing the interface to the W81C180 is as follows: ST = Start (MDA from 1 change to 0 while MCL=1) AW = An acknowledge given by the W81C180 (the W81C180 brings MDA=0 during the 9th MCL pulse.) AU = An acknowledge given by the uC (the uC brings MDA=0 during the 9th MCL pulse.) NA = No acknowledge (this signifies the end of data being read from the W81C180.) SP = Stop (MDA from 0 change to 1 while MCL=1) -5- Publication Release Date: May 1997 Revision A1 W81C180 For example, for the uC to read the W81C180's StatusRegister0 only and the value is E9h: ST 11101001 ST=Start SP=Stop AW SR0 (8) NA SP AU= uC Acknowledge NA=No Acknowledge AW=W81C180 Acknowledge SR0 (8) = Status Register 0 (8 bits) (MSB 1st) 11101001=W81C180's Read Address W81C180 INTERRUPTS: The NINT pin will be enabled and disabled under the following actions: ENABLE INTERRUPT Any USB port (connect/disconnect.) Downstream resume Endpoint 1 data received Endpoint 0 data received Turnaround time-out Suspend (no activity) on the USB bus Reset sent from upstream Babble or loss of data on the USB bus OCP tripped changes DISABLE INTERRUPT status After the uC reads the StatusRegisters. After the uC reads the StatusRegisters. After endpoint 1's FIFO is read. After the uC reads the StatusRegisters. After the uC reads the StatusRegisters. After the uC reads the StatusRegisters. After the uC reads the StatusRegisters. After the uC reads the StatusRegisters. After the uC reads the StatusRegisters. REACTING TO W81C180 INTERRUPTS: Since there is no condition which requires immediate attention by the uC, the NINT pin does not necessarily have to be used. The uC can access the W81C180 in a number of possible ways: - Do not use the NINT pin. Read the Status Register 0 periodically, i.e. every vertical refresh. - Have the NINT pin go to any pin on the uC, poll that pin periodically and read the W81C180 Status registers when it is enabled. - Have the NINT pin go to an interrupt pin to the uC and read the W81C180 Status registers when it is enabled. USB RESET: The W81C180 handles the USB reset function independently from the uC. If a Single Ended Zero (SE0) is detected on the upstream port (port0) for greater then 2.5us, then the SE0 is transmitted to all configured ports and the interrupt is enabled. The uC should then disable all downstream ports, reset its address to 0, and enter the active state. -6- Publication Release Date:May 1997 Revision A1 W81C180 USB SUSPEND: If there is no upstream activity for 3msec then the SUSPEND flag is set and the interrupt enabled. The uC is not required to perform any functions during a USB suspend. The W81C180 stops sending low speed keep alive EOP's when in the suspend state. USB RESUME: The suspend mode can be disabled by a 'resume'. The resume can occur by four methods. - The host can send a resume to all ports by placing a 0 (K state) on the bus. The W81C180 sees the resume, disables the SUSPEND flag, and enables the interrupt. In this case, the uC does not have to perform any functions. - The host can reset the bus. - The uC can initiate a resume by setting URESUME in the Control Register which will cause a K state to be sent to all ports. To un-resume, the uC must clear the URESUME bit in the Control Register. - A downstream port can issue a resume by sending a K state upstream. When the W81C180 senses this K state, it sets the REC_RES flag and interrupt. The uC then has to set the URESUME bit to do a global resume as described above. USB REPEATER: The W81C180 controls the traffic between the upstream (port0) and downstream (ports1,2,3,4) ports without uC intervention. If a 'Start of Packet' SOP is seen on port0, and no other port is transmitting, then the W81C180 will transmit the incoming data to all enabled high speed ports until an 'End of Packet' (EOP) is sent (an EOP is a SE0 for 2 bit times followed by a J state.) The EOP from port0 is sent to the enabled ports as well. If a SOP is seen on an enabled downstream port, any no other port is transmitting, then its data is sent to port0 until an EOP is received which is also sent to port0. USB FRAME TIMER: The W81C180 contains a 1ms timer which is synchronized to the 'Start of Frame' (SOF) packet sent from the host every 1ms. If the W81C180 is waiting for an EOP from a downstream port when the SOF is about to approach, it will disable the port, send an EOP upstream, set the babble/LOA (loss of activity) flag, and enable the interrupt. The uC will then have to unconfigure the port which caused the error, and inform the host via the Interrupt Transfer. BABBLE AND LOST OF ACTIVITY (LOA) If a babble or LOA is found by reading the status registers, then the uC must disable the port which caused it. It must then set the appropriate bit in the Host_Sta byte and send that byte to the endpoint 1 FIFO for the host. The uC will continue to send this byte, after 'DAVEP1' =1, until the host sends a ClearPortFeature via a Control Transfer to the hub's endpoint 0. -7- Publication Release Date: May 1997 Revision A1 W81C180 PORT STATUS: If any downstream port changes state (attached/detached) for >2.5us, then the port flag is set and the interrupt enabled. The uC will then have to inform the host that a change has occurred via endpoint 1. LOW SPEED DETECTION: The W81C180 detects if a port is high speed (HS) or low speed (LS) and sets the appropriate flag. When the port is configured, the uC has to configure it as a HS or LS port and inform the host when asked. The W81C180 will only transmit data from the host to a LS port if the data is preceded by the LS PID and the port is enabled. LOW SPEED KEEP ALIVE: Before every SOF, the W81C180 will transmit two LS single ended zeros (SEO's) to all enabled LS ports, unless the hub is in the suspend mode. USB PHASE LOCK LOOP (PLL): The W81C180's PLL is synchronized to the J-K state from port0 and assures that the data from the host is stored into memory accurately. ABSOLUTE MAXIMUM RATINGS: PARAMETER Supply Voltage (Vcc to Vss) Analog Input Voltage Digital Input Voltage Power Dissipation Ambient Operating Temperature Lead Temperature (Soldering, 10 sec) LIMIT 5.5V Vss-0.5V to Vcc+0.5V Vss-0.5V to Vcc+0.5V TBD 0oC to 70oC 250oC -8- Publication Release Date:May 1997 Revision A1 W81C180 ELECTRICAL CHARACTERISTICS Operating conditions: VCC = 5V +/-5%, Ta=0o to 70oC PARAMETER VCC Supply Current Logic Output High Logic Output Low Logic Input Leakage Current Serial Interface Frequency USB CHARACTERISTICS Leakage Current: Hi-Z State Output Leakage Input Levels: Differential Input Sensitivity Single Ended Signal "0" Differential Common Mode Range Output Levels: Driver Output Low Driver Output High Output Signal Crossover Voltage Capacitance: Transceiver Capacitance Full Speed Timings: PARAMETER Output Rise/Fall Times Source Differential Driver Jitter to Next Transition / to Paired Transition Differential to EOP transition Skew Hub Differential Data Delay(without cable) Hub Differential Driver Jitter to Next Transition / to Paired Transition (including cable) Data bit width distortion after SOP Hub SE0 Delay Relative to t HDD Hub EOP Output Width Skew Note 1: Measured from 10% to 90% of the data signal. Symbol Icc VOH VOL Conditions Min Max TBD Unit mA V V uA Hz Io>24ma Io>6ma Ta=70 C o 2.5 VCC 0.4 10 300k ILO VDI VSE0 VCM VOLU VOHU VCRS CIN Symbol t R /t F t DJ1 /tDJ2 t DEOP t HDJ1 / t HDJ2 t SOP V< V IN <3.3 V |(D+)-(D-)| Includes VDI range RL of 1.5 k to 3.6 V RL of 15 k to GND -10 0.2 0.8 0.8 +10 uA V 2.0 2.5 0.3 V V V V pF Unit ns ns ns ns ns ns ns ns ns 2.8 1.3 3.6 2.0 20 Pin to GND Conditions Note 2, 3 Note 3 Note 2,3,5 Note 3,5 Min -4 /-2 -2 -3 / -1 -5 0 -15 Max 20 4 /2 5 40 3 /1 3 15 15 Note 1, 4 (CL= 50 pF) 4 t HDD2 Note 2,3,5 t EOPD Note 3,5 t HESK Note 3,5 -9- Publication Release Date: May 1997 Revision A1 W81C180 Note 2: Timing difference between the differential signals. Note 3: Measured at crossover point of differential data signals. Note 4: The rising and falling edges should be smoothly transitioning(monotonic) Note 5: Full Speed timing have a 1.5 k pull-up to 2.8 V on the D+ (DP) data line. Note 6: Low Speed timing have a 1.5 k pull-up to 2.8 V on the D- (DM) data line. Note 7: The maximum load specification is the maximum effective capacitive load allowed that meets the target hub VBUS droop of 330 mV. - 10 - Publication Release Date:May 1997 Revision A1 W81C180 TYPICAL APPLICATION: 31 19 VCC 30P X 2 18 9 IN 15K OUT 1 2 12M O P T I O N A L 3.3V REGULATOR 12 13 14 15 1 2 3 4 5 6 7 8 X2 RESET INT0 INT1 T0 T1 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 80C51 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 RD WR PSEN ALE/P TXD RXD 39 38 37 36 35 34 33 32 21 22 23 24 25 26 27 28 17 16 29 30 11 10 EA/VP X1 P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 9 VREF 56K VDD X1 X2 NINT MCL MDA 4 6 5 17 18 19 26 21 22 24 25 23 27 28 30 31 29 1.5K 1 8 1 2 3 4 USB UPSTREAM PORT 2 3 32 V33U VBUS D0M D0P GNDU V33D D1M D1P D2M D2P GND12 D3M D3P D4M GND34 1 2 3 4 16 7 20 NPEN1 OCP1 VSS W82C620 1 2 3 4 USB DOWNSTREAM PORTS 1 2 3 4 OCP SENSE POWER ENABLE IN OUT 1 2 3 4 5V REGULATOR 15K X 8 - 11 - Publication Release Date: May 1997 Revision A1 |
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